...Knowledge of design for reliability (i.e EM, IR etc..)
Knowledge of rules for advanced technology nodes across multiple foundries (SEC, TSMC, GF, Intel)
Knowledge of DFM Rules for advanced technology nodes (16nm and below)
Strong debugging, analytical and trouble shooting...
Title: Analog Design Engineer Location: Anywhere in India
Description:
Good hands on experience in SERDES layout design.
Transmitter, Receiver, PLL kind of blocks
Preferable to have TSMC 3nm experience.
Tool exposure to Cadence and Calibre.
Job Location- Bangalore. Exp.-3+yrs(Industrial experience)
Notice Period- Immediately OR 30days .
Qualification- B.tech/BE
skills-Hands –on experience on TSMC 7nm or below nodes.
...advanced timing closure techniques and methodology
• Knowledge of industry standard tools from Synopsys or Cadence.
• Worked on DSM technologies, tsmc 5nm and below experience preferred.
• Minimum 5+ years of relevant experience
• Good scripting and communication skills...
...Engineer in M-ISS VLSI Design Center
• Proficient in Analog and mixed signal high speed layout designs particularly in process nodes TSMC
3nm, 5nm & Intel 5nm.
• Exposure on knowledge of basic circuits, matching constraints & shielding techniques required for
highspeed...
...performance (timing) and area targets.
~ Expertise in meeting low power design goals would be a plus
~ Experience on 3nm/4nm designs on TSMC/Samsung would be preferred
~ Ability to anticipate / debug the design issues early in the cycle and come up with the solutions....
...checks like FEV, VCLP, EMIR and PV.
• Knowledge of industry standard EDA tools (Synopsys, Cadence, Mentor)
• Worked on DSM technologies, tsmc 5nm and below experience preferred.
• Knowledge of scripting skills.
• Minimum Experience : 5+ years
Location: Bangalore/...
Analog Layout Design Experience - 3+ Years(TSMC 3nm)
Location - Bangalore
Notice period - 0-60 Days
...Physical Design engineering Experience serving as Senior physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m or 16nm process and beyond required
Experience running Synthesis-to-GDS ready flows, advanced timing flows and power-driven PD...
...Experience in Mixed-Signal layouts.
Work Location: Bangalore
Exp: 3+Yrs
Education: B.E./B.Tech. or Masters/M.Tech.
Must have TSMC 3nm, 5nm, 7nm FINFET experience.
Should have worked on Mixed-Signal layout blocks like: High-speed SerDes - Transmitter(Tx),...
...Title: Analog Layout Design Engineers Location: Benguluru, India
Job Description:
Experience in INTEL PDK, Global Foundries PDK, TSMC PDK are acceptable.
Design of LDOs, Bandgaps, Temp Sensors, PLLs, GPIOs and other analog blocks
Design of SERDES blocks like...
...them by working closely with field AEs and R&D teams
Drive customer collaborations with foundries and IP providers as needed (like AMD-TSMC-Synopsys)
Establish excellent relationship with key stakeholders at key customers
Regular 1-1s and visits; Represent BU at...
...lead.
Intimate knowledge of the full design cycle from RTL to GDSII, including chip level.
Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
A solid engineering understanding of the underlying concepts of digital...
...outs
Strong understanding of the full design cycle from RTL to GDSII, including chip level.
Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
A solid engineering understanding of the underlying concepts of digital...
...timely execution with high quality of layout design.
~ Primary Skill set :
~ Analog Layout.
~ Process or technology experience: TSMC – 7nm, 5nm, 10nm,28nm , 45nm,40nm
~ EDA Tools:
~ Layout Editor: Cadence Virtuoso L, XL
~ Physical verification : DRC, LVS, Calibre...