Search Results: 15 vacancies
...functional coverage, basic perl, synthesis, CDC/RDC analysis.
Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....)
Complex high-speed designs for edge computing applications (3.2G HBM PHY, Processor hardening for PPA...
...outs
Strong understanding of the full design cycle from RTL to GDSII, including chip level.
Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
A solid engineering understanding of the underlying concepts of digital...
...Physical Design engineering Experience serving as Senior physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m or 16nm process and beyond required
Experience running Synthesis-to-GDS ready flows, advanced timing flows and power-driven PD...
...performance (timing) and area targets. Expertise in meeting low power design goals would be a plus
Experience on 3nm/4nm designs on TSMC/Samsung would be preferred
Ability to anticipate / debug the design issues early in the cycle and come up with the solutions
Responsibilities...
...in the world
Experience in SOC/IP projects in process nodes 14nm, 10nm, 7nm, 5nm and 3nm (RTL to Tape-out) across multiple foundry TSMC / Samsung
Participated in various SOC and IP designs catering to client processor /server microprocessor /DSP /mobile and IOTG segment...
...related challenges and worked with foundry to negotiate the optimum process and manufacturing cost.Worked with multiple Foundry Vendors TSMC/UMC/Samsung.
Qualifications: ability to identify and analyse tasks efficiently within the scope of your work and to develop...
...lead.
Intimate knowledge of the full design cycle from RTL to GDSII, including chip level.
Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
A solid engineering understanding of the underlying concepts of digital...
...related challenges and worked with foundry to negotiate the optimum process and manufacturing cost.Worked with multiple Foundry Vendors TSMC/UMC/Samsung.
Qualifications : ability to identify and analyse tasks efficiently within the scope of your work and to develop...
...Experience in Mixed-Signal layouts.
Work Location: Bangalore
Exp: 3+Yrs
Education: B.E./B.Tech. or Masters/M.Tech.
Must have TSMC 3nm, 5nm, 7nm FINFET experience.
Should have worked on Mixed-Signal layout blocks like: High-speed SerDes - Transmitter(Tx),...
...Understanding of DFT Constraints.
~ Hand on Synthesis Experience on Lower node Technologies with Synopsys/Cadence Tools. Hands on with TSMC process will be a plus.
~ Hands on Experience on Equivalent Checks with Synopsys / Cadence Tools.
~ Good knowledge on Timing...
...Youll Need:
Have 5+ years experience and will be reporting to Director - ASIC design.
Experience in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm)
Experience Timing Closure/ECOs on block level and chip level in a complex clocking environment including...
...Title: Analog Layout Design Engineers Location: Benguluru, India
Job Description:
Experience in INTEL PDK, Global Foundries PDK, TSMC PDK are acceptable.
Design of LDOs, Bandgaps, Temp Sensors, PLLs, GPIOs and other analog blocks
Design of SERDES blocks like...
...layout towards successful, high-quality, and timely execution
Experience with Finfet process and lower nodes like 2nm/3nm/5nm/7nm in TSMC foundry.
Experience with multiple foundries in lower node eg: Samsung, TSMC, GF.
Experience with Cadence tools (Virtuoso),...
...timely execution with high quality of layout design.
~ Primary Skill set :
~ Analog Layout.
~ Process or technology experience: TSMC - 7nm, 5nm, 10nm,28nm , 45nm,40nm
~ EDA Tools:
~ Layout Editor: Cadence Virtuoso L, XL
~ Physical verification : DRC, LVS, Calibre...
...them by working closely with field AEs and R&D teams
Drive customer collaborations with foundries and IP providers as needed (like AMD-TSMC-Synopsys)
Establish excellent relationship with key stakeholders at key customers
Regular 1-1s and visits; Represent BU at...
