Search Results: 12 vacancies
Job Location- Bangalore. Exp.-3+yrs(Industrial experience)
Notice Period- Immediately OR 30days .
Qualification- B.tech/BE
skills-Hands –on experience on TSMC 7nm or below nodes.
...Knowledge of design for reliability (i.e EM, IR etc..)
Knowledge of rules for advanced technology nodes across multiple foundries (SEC, TSMC, GF, Intel)
Knowledge of DFM Rules for advanced technology nodes (16nm and below)
Strong debugging, analytical and trouble shooting...
Title: Analog Design Engineer Location: Anywhere in India
Description:
Good hands on experience in SERDES layout design.
Transmitter, Receiver, PLL kind of blocks
Preferable to have TSMC 3nm experience.
Tool exposure to Cadence and Calibre.
...Title: Analog Layout Design Engineers Location: Hyderabad, India
Job Description:
Experience in INTEL PDK, Global Foundries PDK, TSMC PDK are acceptable.
Design of LDOs, Bandgaps, Temp Sensors, PLLs, GPIOs and other analog blocks
Design of SERDES blocks like...
...for timely execution with high quality of layout design.
Primary Skills
Analog Layout
Process or technology experience: TSMC – 7nm, 5nm, 10nm,28nm , 45nm,40nm
EDA Tools:
Layout Editor: Cadence Virtuoso L, XL
Physical verification : DRC, LVS, Calibre...
...Physical Design engineering Experience serving as Lead physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m process and beyond required
Experience running Synthesis-to-GDS ready flows, advanced timing flows and power-driven PD flows (e....
...Experience in Mixed-Signal layouts.
Work Location: Bangalore
Exp: 3+Yrs
Education: B.E./B.Tech. or Masters/M.Tech.
Must have TSMC 3nm, 5nm, 7nm FINFET experience.
Should have worked on Mixed-Signal layout blocks like: High-speed SerDes - Transmitter(Tx),...
Analog Layout Design Experience - 3+ Years(TSMC 3nm)
Location - Bangalore
Notice period - 0-60 Days
...outs
Strong understanding of the full design cycle from RTL to GDSII, including chip level.
Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
A solid engineering understanding of the underlying concepts of digital...
...GDS2
• Analog/Mixed/Custom Signal PNR experience preferred to help drive partitioning for digital and mixed signal SoCs
• Preferably TSMC 7nm PNR sign-off experience using a full COT flow from RTL/gate to GDS
• Experience in developing PNR methodology/flow to and...
...lead.
Intimate knowledge of the full design cycle from RTL to GDSII, including chip level.
Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
A solid engineering understanding of the underlying concepts of digital...
...them by working closely with field AEs and R&D teams
Drive customer collaborations with foundries and IP providers as needed (like AMD-TSMC-Synopsys)
Establish excellent relationship with key stakeholders at key customers
Regular 1-1s and visits; Represent BU at...
