Average salary: Rs64,530 /yearly

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Search Results: 55 vacancies

 ...STA Design Engineer at Semiconductor product MNC design center. We need experienced Static Timing Analysis engineers to design and...  ...making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team... 

Sevya Multimedia

Hyderabad
2 days ago
 ...experience in Verilog and/or VHDL coding. ~ Must have experience in synthesis and implementation (floor planning and placement and routing)...  ...a major plus. ~ Thorough knowledge of Static Timing Analysis (STA) is an added advantage. ~ Must have experience in building test... 

Skyroot Aerospace

Hyderabad
11 days ago
 ...Own RTL Quality Checks: Clock Domain Crossing (CDC) check, Lint, etc. Design for Testability (DFT) checks Low Power Checks RTL Synthesis and STA support Pre and Post Silicon functional verification support Close collaboration with different domain teams.... 

Renesas Electronics

Hyderabad
5 days ago
 ...implementation engineers and have personal design responsibility, including synthesis, floor planning, power grid design, place and route, clock tree...  ...and models. Good understanding of static timing analysis (STA), EM/IR and sign-off. Strong hands-on experience with: Chip... 

Mulya Technologies

Hyderabad
3 days ago
 ...processors like RISC-V and ARM processors Knowledge of design signoff flows including Lint, CDC, Formal Verification, Synthesis, Constraints and STA Timing Closure Knowledge of DFT including Scan, ATPG, MBIST Knowledge of low power design methodology (static/dynamic... 

Silicon Labs

Hyderabad
18 days ago
 ...Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test · Strong understanding of relationships between Hardware, Firmware... 

MosChip

Hyderabad
more than 2 months ago

Rs 6 - 20 lakhs p.a.

 ...* Timing closure  * Multimode multi corner optimization and closure.  * Clock tree synthesis and advanced clock tree implementation.  * Block level timing closure with sign off STA . * Block level ECO implementation involving netlist level logical changes.  * Library... 

Fizara India Pvt Ltd

Secunderabad
more than 2 months ago
 ...the block level, particularly at 16/7nm technology nodes. Key responsibilities include floor planning, clock tree synthesis (CTS), static timing analysis (STA), physical verification, and a basic understanding of timing constraints. Additionally, familiarity with ICC2, Innovus... 

Kiash Solutions LLp

Hyderabad
4 days ago
 ...of design flows, including floorplanning, placement, Clock Tree Synthesis (CTS), routing, crosstalk avoidance, physical verification (DRC/LVS...  ...to constraints validation, verification, Static Timing Analysis (STA), and Physical design.- Utilize Tcl/Perl scripting for automation... 

ACL Digital

Hyderabad
4 days ago
 ...including data preparation, floorplanning, placement, clock tree synthesis, routing, timing and DRC closure, and low power/multi-voltage physical...  ..., Design Compiler, Genus), Tool knowledge (preferred): STA (Primetime, Tempus) Inclusion and Diversity are important to... 
Hyderabad
more than 2 months ago
 ...Ethernet) is highly desirable. ~ Knowledge in Verilog/VHDL coding, Spyglass LINT/CDC/RDC checks and waiver creation. ~ Knowledge in Synthesis, STA, Formal checking, etc. ~ Knowledge in Verification and debugging issues. ~ Understanding of RTL to GDS flow. ~ Familiarity... 
Hyderabad
more than 2 months ago
 ...of the product at all different levels (logic and architecture, synthesis and P&R flows, floorplan, libraries, technology selection) Run...  ...Participate in power and area budgeting and scoping activities. Perform STA to ensure design meets timing across multiple corners and... 
Remote job

Edgecortix Inc.

Hyderabad
5 days ago
 ...lead role.  With 10+ years of experience. --  Proficiency with Synthesis, timing closure and industry standard tool flows like Fusion Compiler...  ...is an additional value add. --  Static Timing Analysis (STA) exposure is desirable. --  Working with cross-functional teams... 
Hyderabad
more than 2 months ago
 ...to bring it within limits Actively drive Service & Product Leads for assigned technician group within service area by implementing STA (See, Tell, Ask) and T.I.M.E. (Train, Incentivise, Monitor, Engage) on the job coaching to create density of customers. Innovation:... 

Rentokil Initial

Hyderabad
3 days ago
 ...in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. - Experience in modifying STA constraints to check timing closure feasibility Have hands-on experience in latest sub-micron technologies below 10 nm • Hands –on... 

ProConnxt

Hyderabad
26 days ago
 ...instrumental in shaping how we do it with your ideas, thoughts, and solutions. Your Impact Champion the discovery, research, and data synthesis to identify critical user insights and develop hypotheses to design effective experiences. Communicate with excellent aesthetic... 

uxin

Hyderabad
8 days ago
 ...interpersonal, verbal/written communications, problem solving and decision-making skills Traits: Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency. Solutions... 

Sevya Multimedia

Hyderabad
2 days ago
 ...requirements document. Define FPGA interfaces with other circuitry along with hardware design engineer. Do FPGA programming, synthesis and simulation, timing analysis and optimization. Validate system along with the hardware and firmware design engineers to confirm... 

Talent Leads HR Solutions Pvt Ltd

Hyderabad
8 days ago
 ...like clocking, reset, memory map, hierarchical bus interconnect Knowledge of IP and SoC design flows and methodologies (Lint, CDC, Synthesis, power). Ability to work with local and remote teams (Architecture, DV, DFT, and Physical Design) Proficient in EDA tools used... 

Sevya Multimedia

Hyderabad
16 days ago
 ...methodologies including simulation, GLS and Formal techniques. Candidate will require close interactions with Design, SoC , Validation, Synthesis & PD teams for design convergence. Candidate must be able to take ownership of IP/Block/SS verification. He/She will work with... 

Silicon Labs

Hyderabad
a month ago