Search Results: 14 vacancies
...A "Full Chip STA Lead" is a key role in semiconductor companies, responsible for leading Static Timing Analysis (STA) activities for... ...including understanding of setup and hold time violations, clock tree synthesis (CTS), and optimization techniques.
# CDC and SI Analysis:...
...partitioning, interface definitions, and data paths.
# Coding and Synthesis: Write RTL code using hardware description languages such as... ...constraints, clock domain crossing issues, static timing analysis (STA), and timing closure methodologies to meet design timing...
...physical design flow, including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
#... ...Expertise in timing closure techniques, static timing analysis (STA), clock domain crossing (CDC) analysis, and timing convergence...
...optimize performance, power, and area (PPA) metrics.
# Clock Tree Synthesis: Assist in clock tree synthesis (CTS) to ensure proper clock... ...Work on timing closure tasks, including static timing analysis (STA), to meet timing constraints and achieve desired performance targets...
...to meet design rules and performance requirements.
# Clock Tree Synthesis: Design and optimize clock trees for synchronous designs,... ...design goals.
# Timing Closure: Perform static timing analysis (STA), identify timing violations, and implement optimizations such as...
...performance, minimize area, and ensure signal integrity.
# Clock Tree Synthesis (CTS): Design and optimize clock distribution networks to... ...Experience with timing closure techniques such as static timing analysis (STA), clock skew optimization, and hold time fixing.
# DFM and...
...logic design aspects ranging from RTL to timing/power convergence.
o Hands on experience in running Synopsys Fusion Compiler for Synthesis and Area and performance estimation
o Perform RTL Lint check, Equivalence checking, CDC checking and support Static Timing Analysis...
...methodologies.
# Design Tools: Proficiency in using industry-standard design tools and software for microarchitecture design, simulation, synthesis, and verification, such as Verilog, VHDL, SystemVerilog, Cadence, Synopsys, and Mentor tools.
# Programming Skills: Strong...
...Design Flow: Define and optimize the physical design flow, including floor planning, power planning, placement, routing, clock tree synthesis, and timing closure, to meet design goals and performance targets.
# Design Methodology: Implement and improve physical design...
...# PnR Flow Development: Define and optimize the place and route (PnR) flow, including floorplanning, power planning, clock tree synthesis, placement, routing, and optimization techniques.
# Timing Closure: Lead timing closure efforts by analyzing and addressing timing...
...constraints, area constraints, and power constraints to optimize the RTL design for performance, area efficiency, and power consumption.
# Synthesis and Optimization: Work with synthesis tools and optimization techniques to generate optimized netlists from RTL descriptions,...
...understanding of SoC or full-chip design principles, methodologies, tools, and technologies, including knowledge of RTL design, verification, synthesis, physical design, and validation.
# Communication and Leadership: Excellent communication, leadership, and interpersonal skills...
...and compatibility.
# Timing Closure: Collaborate with timing engineers to achieve timing closure and meet performance targets.
# Synthesis and Optimization: Work with synthesis tools to optimize and improve design performance, area, and power consumption.
#...
...Microarchitecture: Develop microarchitectural specifications, block diagrams, and RTL coding guidelines for efficient and scalable designs.
# Synthesis and Optimization: Optimize RTL code for area, timing, and power using synthesis tools and techniques, and collaborate with physical...
