Search Results: 21 vacancies
Job Description
Job Details: Job Description: Looking for a passionate engineer for solving problems around FEV and functional ECO in ASIC structural design. He/She will be working on IFS customer ASIC designs on latest intel tech nodes to execute full chip logic equivalence...
...Transformation space, is seeking a skilled Design Engineer specializing in STA (Static Timing Analysis), SD (Signal Integrity), Power, and PDN (Power Delivery Network) to join our team. Working with Fortune 500 companies to support their digital innovation and transformation...
...field theory.
Preferred Qualifications:
�Good understanding on various droop mitigation schemes, Verilog level modeling, On-chip PDN and circuit techniques, PDN to timing correlation, CAD tools - Cadence Virtuoso, Spectre, Solid scripting skills in Python/tcl.
Requirements...
...beneficial.
Understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre and ICV.
TCL/PERL Scripting is plus.
Hands on experience :Innovus/Fusion Compiler , Tech lef is preferable.
People management /Floorplanning/Power Planning/PDN experience is BIG Plus...
...Participate on a project involved in the development of ASICs, with emphasis in Static Timing Analysis(STA), Power Distribution Network(PDN) Analysis, Power Estimation, Place and Route, Low Power Implementation and Physical Verification.
· Create design of experiments and...
...vendors, managing the End of Life (EoL) for mechanical components including analyzing Product Change / Discontinuation Notification (PCN/PDN) & recommending solutions.
Should have solid understanding of various environmental regulations like RoHS, WEEE, REACH, PFAS, POP...
...(e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.).
· Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced...
...and STA flows Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting Principal Duties and responsibilities: Complete...
...STA flows
Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc
Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc
Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting
Principal Duties and responsibilities:
Complete...
...understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience
~ In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through...
...flows such as Synthesis, Floorplan, Placement, CTS, Route/ECOs using industry standard tools.
Candidate must be proficient with STA, PDN, PDV, Logic ECOs and Chip Sign-off.
Can – do attitude, openness to new environment, people and culture.
Must be proficient on low...
...the open positions!!!
STA : 4+ Years
Experience in chiptop / Top Level / Block level / Fullchip /
#Tweaker #Tempus#Primetime
#PDN/ #IR_Drop/ #EMIR : 3+ Yrs
Voltas, Redhawk_SC, EMIR, Power integrity
Physical Design: 4+ Yrs
Experience in Block level /...
...Bangalore with the following: - Ideal candidate will have 4 to 9 years of experience in EM/IR - Mandatory to have tape-out experience as PDN block owner/Lead. - Experience in Power Estimation, Power Grid Planning & Closure. - Expert in EM/IR Analysis and Signoff using Ansys...
...signal propagation and interference analysis
LTE Architecture, Core understanding (Adding IMSIs, Wireshark capture on interfaces, Adding PDN routes)
Experience / Skill Required:
Exp – 3 to 7 yrs
LAN network
Basic knowledge on IP core network related to the 4G...
...implementation flows such as Synthesis, Floorplan, Placement, CTS, Route/ECOs using industry standard tools.
Familiarity with STA, PDN, PDV, Logic ECOs and Chip Sign-off is a plus
Must be cognizant about low power implementation techniques.
Can – do attitude; openness...
...signoff for high speed cores.
~ Should have good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology.
~ Masters/Bachelors Degree in Electrical/Electronics science engineering with at least 7+ years of experience in IC...
...Graphics / Altium
# Experience of interaction with PCB fabrication house and assembly house for hardware build.
# Design analysis for SI, PDN, Thermal, EMI/EMC
# Product qualification / Compliances test experiences .
Skills Required : Hardware Board Design, High Speed...
...Mentor Graphics
Experience of interaction with PCB fabrication house and assembly house for hardware build.
Design analysis for SI, PDN, Thermal, EMI/EMC.
Experience in quality product release to customers.
Technical Management Skills:
Technical management with...
...Physical Design and Optimization
Timing Closure and Signal Integrity
Clock Tree Synthesis (CTS) and Power Distribution Network (PDN)
Physical Verification, Formal Verification
Technology Node Migration
Multi-Voltage Design, Hierarchical Design, and IP Integration...
...and optimize clock distribution networks to achieve low skew, high frequency, and low power consumption.
# Power Distribution Network (PDN): Design and optimize power grids to deliver clean and stable power to IC components while minimizing IR drop and voltage noise.
#...
