Search Results: 3 vacancies

 ...background in RTL design and a deep understanding of frontend design tools and flows. Responsibilities: Develop RTL code for advanced ASIC designs. Collaborate with architects and engineers to meet design specifications. Optimize RTL code for area power and... 

pooja

Bhubaneswar
26 days ago
 ...Proficiency in Verilog/ System Verilog and experience with industrystandard verification methodologies (OVM/UVM). Strong understanding of ASIC design flow and verification techniques. Excellent problemsolving and debugging skills. : Experience with formal verification... 

ARF

Bhubaneswar
a month ago
 ...lightweight CPU or microcontroller designs and operation fundamentals Exposure to backend implementation and signoff in STA, P&R, and RTL2GDS ASIC flows Demonstrated technical expertise in the productization of advanced technologies Experience with yield analysis to drive... 

Synopsys Inc

Bhubaneswar
a month ago