Design Engineer - Remote

Experience: 3.00 + years

Salary : INR 2680000-3750000 / year (based on experience)

Shift : (GMT+05:30) Asia/Kolkata (IST)

Opportunity Type : Remote

Placement Type : Full Time Permanent position(Payroll and Compliance to be managed by: emulation, Flexibility, tapeout, Data Analysis, Verilog/System-Verilog, RTL, synthesis, Unit Level testing, Python, typescripts, SoC integration

As a RTL/Design Engineer at Architect Labs , you'll redefine the hardware design and verification process, methodology, and tools using our proprietary AI models and systems. In that context, we are seeking mid-level front-end hardware engineers to help build and curate high-quality RTL and verification datasets for AI training and evaluation. You'll work on reviewing, debugging, coding, labeling, and generating Verilog/SystemVerilog designs, unit-level testing, and POC design development and verification.

Write, review, debug+fix and annotate code, waveform, specs, and hardware documents for model training and evaluation datasets.

Design & validate modular RTL designs (FIFOs, ALUs, NoCs, etc.) using our models and tools to advance our AI-enabled IP generation efforts.

Curate, document, and label RTL bugs, coding methods, and architectural definitions.

Help in prompt-tuning, generating rules and guardrails for our RTl coding agents and models.

Collaborate with ML engineers to build evaluation datasets, internal benchmarks, and evaluate model behavior and performance on RTL code.

Log quality metrics and tabulate for functionality, syntax, style, and completeness.

Partner with architects, validation engineers for documentation of in-house design.

Develop POC designs, partnering with architects, validation, and AI engineers

Synthesize eval & POC designs, own hand-off-to-backend quality convergence.

Bachelor''s (or more) degree; 3+ years experience in RTL design (SystemVerilog).

Experience in end-to-end design flow - design, linting, ULT and synthesis,

Automation(Python, etc) skills for scoping & templatizing design flows and tasks.

Familiarity with SoC integration and design principles.

Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field from a Tier-1 institution (IITs, IIITs, BITS Pilani, NIT Trichy/Surathkal/ Warangal, etc.).

Strong academic and research orientation is a plus.

Experienced in at least one product-level tape-out.

Data analytics skills, data annotation experience.

Bonus if graduated from a top university like IIT, VIT, IISC, SRM, BITS, etc.

You'll work remotely from India but collaborate daily with the Palo Alto team.

Must have excellent written and spoken English communication, clear, concise, and proactive.

Technical R1 (Code writing)

Technical R2 (Technical discussions + Live Coding + Behavioural)

Step 3: Increase your chances to get shortlisted & meet the client for the Interview!

Our role will be to help all our talents find and apply for relevant contractual onsite opportunities and progress in their career. So, if you are ready for a new challenge, a great work environment, and an opportunity to take your career to the next level, don't hesitate to apply today.