Search Results: 216 vacancies

 ...years of design and development experience, preferably in a customer facing role Minimum of 3 years of experience in FPGA VHDL and/or Verilog design, Xilinx technology and tools, FPGA verification and test Experience in writing technical documentation, including... 

Xilinx

Secunderabad
1 day ago
 ...RESPONSIBILITES POSITION TITLE: Technical Lead – ASIC Design Verification LOCATION:...  ...· Minimum 6 years of experience in System Verilog HVL. · Minimum 6 year of experience in OVM...  ...· B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation... 

eInfochips (An Arrow Company)

Hyderabad
18 days ago
 ...in Design Verification- Must have experience in creating Verification Plans for SOCs And IP Blocks- Must have experience With System Verilog, UVM Reuse Methodology- Experience With Advanced Verification Techniques Like Constrained Random Generation, Functional Coverage, Assertions... 

MY Search

Hyderabad
4 days ago
 ...Engineering, Electronics and Telecommunication Engineering branches or any VLSI and Microelectronics related. # The candidate should have...  ...viz. UVM, OVM, VMM. # Knowledge on HDL's preferably Verilog and system Verilog is a must. # Fundamentals of protocols (PCIe... 

Synopsys India Private Limited

Secunderabad
20 days ago
 ...SoC integration, and backend teams throughout various stages of ASIC development. Qualifications ~8+ years of experience in UVM...  ...plan definition and testcase development in C/Assembly/System Verilog ~ Expertise in verifying design at RTL level and gate-level simulation... 

Axiado

Hyderabad
19 days ago
 ...information on Interface IP Subsystems @ We're looking forSenior ASIC Digital Design Managerto join Synopsys Solutions Group, Digital...  ...interface protocols. -- Programming skills such as System Verilog, TCL, Perl or Python. -- The ability to motivate the team and drive... 

Sypnosys

Secunderabad
1 day ago
ASIC Verfication Engineer Lead ~8 to 15 years of experience in SOC/IP/block level functional verification using System Verilog/UVM. ~ Strong knowledge of UVM, advance UVM,System Verilog. ~ Must have worked on development of testplan, testbench components, verification... 

Kiash Solutions LLP

Secunderabad
10 days ago
 ...we invite you to apply for this job. Job Description ASIC/SoC Design  position is your opportunity to join one of the industry...  ...specifications; ~ Expertise in writing efficient RTL code in Verilog and SoC integration ~ Good understanding of assertions,... 

Axiado

Hyderabad
13 days ago
 ...Bachelor's/Master's/Ph.D. degree in Electronics and communications (VLSI) Strong understanding of analog and mixed-signal circuit design...  ...in verification methodologies and tools such as SystemVerilog, Verilog-A, Verilog-AMS, and Cadence Virtuoso. Experience with... 

Modernize Chip Solutions Pvt. Ltd

Hyderabad
2 days ago
Job Description :- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.- At...  ...concept to verification closure.- Strong hands-on UVM and System Verilog coding experience and functional verification environment development... 

Digicomm

Hyderabad
4 hours agonew
 ...communicate and advance faster than ever. JR49460 Senior Engineer - ASIC Design BS/MS in E&E or related field with 6+ years of...  ...integration. Strong fundamental knowledge of digital design, Verilog, system Verilog and scripting languages Deep knowledge of IP and... 

Micron

Secunderabad
1 day ago
 ...protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols. --- Programming skills such as System Verilog, TCL, Perl or Python. --- The ability to work independently, precisely and to drive innovation --- The ability to extract detailed... 

Sypnosys

Secunderabad
1 day ago
 ...capable of thoroughly verifying the NVM IP.Qualifications and Experience :- Bachelor's or Master's degree.- 3 to 7 years of experience in ASIC or FPGA verification, with a focus on SV/UVM methodology.- Experience in developing SV/UVM testbenches for complex IP verification,... 

Troy Consultancy

Hyderabad
4 hours agonew
 ...and growth opportunities. Key Qualification: BS/MS in EE/EC/VLSI stream with 4+ years of relevant experience in the verification...  ...or SOC. Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans... 
Hyderabad
more than 2 months ago
 ...gating, power gating, dynamic voltage and frequency scaling). ~ Testability experience of Test Modes, DFT, MBIST and BScan. ~ VLSI implementation experience in synthesis, timing analysis, Design for Test and Memory BIST. ~ Senior positions require experience of... 

Ceremorphic Inc

Secunderabad
a month ago
 ...protocols (PCIe/Ethernet) is highly desirable. ~ Knowledge in Verilog/VHDL coding, Spyglass LINT/CDC/RDC checks and waiver creation....  ...creative way Helping verification team to debug the issue Running ASIC development tools including Lint and CDC Guides junior peers... 

Sypnosys

Secunderabad
1 day ago
 ...protocols AMBA (APB, AXI, CHI), DDR/PCIe/Ethernet/USB/UFS and other interface protocols. --- Programming skills such as System Verilog, TCL, Perl or Python. --- The ability to work independently, precisely and to drive innovation --- The ability to extract detailed... 

Synopsys India Private Limited

Secunderabad
17 days ago
 ...Design and architect testbenches in System Verilog and UVM to complete verification of the...  ...Strong understanding of different phases of ASIC and/or full custom chip development is required...  ...for high performance FPGAs, SOCs and/or VLSI designs is a plus. Experience with gate... 

Xilinx

Secunderabad
1 day ago
 ...Bachelor's degree in Computer Engineering, Computer Science, or equivalentMinimum 5 years of FPGA design experienceProficiency in VHDL/Verilog programmingKnowledge of embedded systems and communication protocols (AXI, I2C, SPI, UART, Ethernet)Familiarity with debugging tools... 

TekPillar

Hyderabad
4 hours agonew
 ...industry experience with 2+ years in RTL Design and SoC Integration. Proven hands-on experience with RTL design for IP, the subsystem for ASIC. Hands-on experience with SoC integration issues like clocking, reset, memory map, hierarchical bus interconnect Knowledge of IP... 

Sevya Multimedia

Hyderabad
11 days ago