Average salary: Rs801,557 /yearly

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Search Results: 20,058 vacancies

 ...be part of a highly skilled ASIC Team working on the Latest Technology Nodes.- Responsible for Technically Leading & Managing an overall IP/SS Verification from Test-Plan creation, UVM development to Signoff.- Ensure first pass product through multi-dimensional Verification... 

ConnectPro Management Consultants Pvt Ltd.

Bangalore
2 days ago
 ...Prodapt is looking for a Verification Lead/ Manager with hands-on experience in VLSI front end Verification Experience in developing the TB for verification of a complex design bloc using system verilog and UVM methodology. Excellent debug skill. Should have experience... 

Prodapt

Bangalore
4 days ago
 ...on experience on design data analysis Experience on design verification and validation Knowledge on CBTC systems will be an added advantage...  ...handling projects independently Overall project life cycle management   Required Experience / Skill Set Possess advance... 

Alstom

Bangalore
1 day ago
 ...Analog Devices is seeking a senior Mixed Signal Design Verification Engineer who will be responsible for design verification of highly integrated...  ...of Analog/Mixed-Signal/RF building blocks such as Power Management, ADCs, DACs, PLL, bandgap references, oscillators, SerDes, RF... 

Analog Devices

Bangalore
10 days ago
 ...provider, is seeking to hire an exceptional Senior/Principal Design Verification Engineer to join our PCIe Express IP Products team in...  ...position, reporting in thru to the BU Verification director & management.   Rambus offers a flexible work environment, embracing a hybrid... 

Rambus

Bangalore
8 days ago
 ...industry, and our technically competent team of 300+ engineers and management consultants deliver impeccable results to onsite and offsite...  ...Role Description This is a full-time on-site role for a Verification Validation Engineer located in Bengaluru. The Verification Validation... 

SARACA

Bangalore
1 day ago
 ...coverage, DC & CC • RTRT/LDRA/any other tools • Project exposure to test bench & simulators • Knowledge on configuration & change management • System/Software Requirement Analysis • Develop/Update system/software level test case/procedures. • Test execution and... 

Applycup Hiring Solutions | Top Recruitment & Staffing Agenc...

Bangalore
1 day ago
 ...Verilog Methodology: UVM (preferred), OVM, VMM. Knowledge of scripting (Perl, C-shell) SVA will be a plus Good general verification experience with good academy results. Must-Have: SoC or IP Experience Languages: System Verilog Methodologies: PCIE/OVM/UVM... 

Mirafra Technologies

Bangalore
9 days ago
 ...Hiring DV Engineers! Experience: 5-15 years Location: Kochi/Ahmedabad/Bangalore/Vizag · Design verification of IP-level, SoC -level and/or block-level/sub-system-level designs · Experience in developing verification plan/verification methodology/flows from scratch... 

Tech Mahindra

Bangalore
9 days ago
 ...Quest Global Title :: Physical Verification Engineer Location :: Bangalore, India Below is the job description :: ~[( 7nm and below exposure, preferred 3nm)] ~ Own physical convergence(DRC/LVS/ERC/softcheck/ESD/PERC) closure of a complex subsystem in PnR and calibre... 

Synapse Design Inc.

Bangalore
9 days ago
 ...invite exceptional talent like yourself, to join our Technical team at Harman. Job Description: Location: Bangalore Design Verification with SV, UVM & Ethernet IP expertise – Persson should be able to create test plans & develop test benches from scratch. 5-10yrs... 

HARMAN India

Bangalore
1 day ago
 ...JOB DESCRIPTION Title/Position: CPU Verification Engineers/Leads/Manager Location: PAN India Positions: 20 Type: Fulltime Interested candidates please share the CV to ****@*****.*** CPU Verification Engineers/Leads/Manager This... 

Tessolve

Bangalore
4 days ago
 ...Job Description: Roles & Responsibilities: Exp- 12 - 16 yrs The role requires the management of a SerDes DV group focusing on MDV verification including: Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship... 

Cadence Design Systems

Bangalore
a month ago
 ...Description Role: Software Engineer Total experience : 57 years Location: Bangalore Category: R&D : Software Integration & Verification Mandatory skill set required : Excellent knowledge on various Mobile Radio Access Technologies such as LTE LTEAdv. & IMS.... 

eictechsys

Bangalore
15 days ago
 ...,000 world-class talents, Eviden expands the possibilities of data and technology, now and for generations to come. Title: ASIC Verification Engineer Location: Bangalore (Whitefield) Experience: 3-5 years Education: Bachelor’s degree (B.E./B.Tech) or Master’s degree... 

Atos

Bangalore
2 days ago
 ...better decisions quicker on the most trusted hardware platform in today’s market. Your Role and Responsibilities As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the... 

IBM

Bangalore
20 hours ago
We are hiring on immediate basic for below skills (NP - 0 to 30days). Design Verficiation (IP) - 3+ yr exp Design Verification (SoC) - 3+ yrs exp FPGA Validation - 3+yrs exp Analog desing engineer - 5+ yrs exp DV with CAD - 3+yr exp

LeadSoc Technologies Pvt Ltd

Bangalore
6 days ago
 ...experience and eager to learn advanced Complete IP/SOC Front End Design techniques. Position: Design Verification (Design /Sr. design Engineer/Design Lead /Sr. Design Lead/Manager/Sr. Managers) Experience: 5 years to 25 years relevant experience. Location - India and... 

Tessolve Semiconductor Pvt. Ltd.

Bangalore
9 days ago
 ...Engineering or equivalent practical experience 7/10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification 7/ 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies... 

L&T Technology Services

Bangalore
9 days ago

Rs 50 lakh p.a.

 ...Salary : Upto Rs 50 LPA Key Skills: Pre Silicon Design Verification UVM test Benches Key responsibilities verification requirements...  ...junior engineers verification metrics, status and risks to management test suites (SV/UVM, C, etc, as needed) and test benches... 

M/s Angel and Genie

Bangalore
1 day ago