Search Results: 8 vacancies
...Physical Design Flow: Define and optimize the physical design flow, including floor planning, power planning, placement, routing, clock tree synthesis, and timing closure, to meet design goals and performance targets.
# Design Methodology: Implement and improve physical...
...infrastructure performance diagnosis and scalability assessment activities- In-depth knowledge of layer 2 technologies, such as Vlans, Spanning-Tree, MLAG, MEC, VXLAN and MPLS.- Central Authentication, Authorization and Accounting protocols such as RADIUS or TACACS+- Display their...
...Closure: Expertise in achieving timing closure for full-chip designs, including understanding of setup and hold time violations, clock tree synthesis (CTS), and optimization techniques.
# CDC and SI Analysis: Experience in clock domain crossing (CDC) analysis, signal...
...timing goals.
# PnR Flow Development: Define and optimize the place and route (PnR) flow, including floorplanning, power planning, clock tree synthesis, placement, routing, and optimization techniques.
# Timing Closure: Lead timing closure efforts by analyzing and...
...Responsibilities:
# Physical Design Flow: Lead and execute the complete physical design flow, including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
# Design Implementation: Implement high-performance and low-...
...Perform block-level and chip-level placement and routing to optimize performance, minimize area, and ensure signal integrity.
# Clock Tree Synthesis (CTS): Design and optimize clock distribution networks to achieve low skew, high frequency, and low power consumption.
#...
...Routing: Participate in placement and routing tasks using automated tools to optimize performance, power, and area (PPA) metrics.
# Clock Tree Synthesis: Assist in clock tree synthesis (CTS) to ensure proper clock distribution and timing closure across the IC.
# Power Grid...
...to achieve timing, area, and power targets, and execute detailed routing to meet design rules and performance requirements.
# Clock Tree Synthesis: Design and optimize clock trees for synchronous designs, considering skew, jitter, and power considerations.
# Power Planning...
