Search Results: 7 vacancies
We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer with 5-10 years of experience in digital ASIC design and timing closure. As a Senior STA Engineer, you will play a key role in ensuring the timing integrity and performance of our advanced semiconductor...
...experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.
Good exposure in Floor planning CTS STA Physical Verification Basic understanding of timing constraints.
Good exposure to ICC2/Innovus/Calibre/Formality/LEC tool set....
...clock tree synthesis (CTS), routing, and optimization.- Timing Closure : Ensure timing closure using advanced static timing analysis (STA) techniques and tools.- Power and Area Optimization : Optimize designs for power, performance, and area, considering factors such as power...
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Good exposure to industry standard Physical design tools (place & route) & methods, timing analysis using static timing analysis (STA) tools.
Must have very good written & oral communication skills, ability to motivate team members to do innovation in the area of DFT...
...tools
Provide expert advice and support to configure and resolve IP integration challenges including simulation, synthesis, floorplan, STA, DFT and silicon bring-up
Provide integration training to customers and conduct reviews on their major SoC milestones
Provide...
...experience in Physical Design Implementation & Signoff at block level at 16/7nm technology nodes.- Good exposure to Floor planning, CTS, STA, Physical Verification, and Basic understanding of timing constraints.- Good exposure to ICC2/ Innovus / Calibre / Formality / LEC...
...with 3+ years of experience
Strong understanding of ASIC digital design flow with command on
RTL design using HDL
Synthesis & STA
CDC/RDC analysis and understanding
Exposure to Serial interface protocols and designs
Our Silicon IP business is all about...
