...ASIC Design - Verification - Physical Design - DFT - Circuit Design & Layout - FPGA Design and EmulationThey are looking for Deep Sub Micron Analog Circuit Design to be based at Hyderabad with the following:- Total 5 to 10 years of experience with 5+ years of experience in analog... 

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Hyderabad
12 days ago
 ...others along with industry collaborations with Schneider Electric, FESTO, Automotive Skills Development Council (ASDC), AM/NS India and Micron to name a few. NAMTECH is hiring for multiple positions: Professor and Program Directors: • Semiconductor Manufacturing Program •... 

NAMTECH

Gandhinagar
2 days ago
 ...cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. Strong knowledge of ultra-deep sub-micron layout design related challenges and good understanding of DFM guidelines. Experience & or strong interest in memory compilers... 

UST GLOBAL TECHNOLOGY SERVICES (INDIA) PRIVATE LIMITED

Bangalore
14 days ago
 ...from specs, perform required feasibility checks, design, and implement and validate mixed-signal Integrated Circuits (ICs) in deep sub-micron CMOS/FINFET technologies for high-speed transceiver modules. Work across teams to establish design requirements and block... 

Analog Devices, Inc

India
3 days ago
 ...design Implementation RTL to GDSII : Synopsys/Cadence tools. � Familiar with LVF/POCV variation formats and understanding of deep sub-micron topics especially 28nm and below technology nodes. � Handson experience on timing closure industry standard high speed interfaces like... 

Intel Corporation

Bangalore
3 days ago
 ...independently in different phases of the RTL2GDS flow along with PV and IR/EM. Take physical limitation of hierarchical deep sub-micron FinFET designs into account. Tap your experience to contribute significantly to the hierarchical SoC architecture... 

Infineon Technologies AG

Bangalore
18 days ago
 ...qualification: ----------------------------Good knowledge on CMOS device physics. -Understanding of basic circuit and layout blocks in deep sub-micron CMOS/FinFET technology. -Exposure to basic analog layout blocks in Cadence Virtuoso tool environment, exposure to Synopsys Custom... 

Intel Corporation

Bangalore
3 days ago

Rs 20 - 22 lakhs p.a.

 ...coverage analysis, functional coverage, basic perl, synthesis, CDC/RDC analysis. - Experience in STA for block & top level in deep sub-micron tech nodes (TSMC 6nm, 7nm, GF12, TSMC 12nm,....) - Complex high-speed designs for edge computing applications (3.2G HBM PHY,... 

ISoftronics | Recruiting, Staffing And Consulting

Bangalore
15 days ago
 ...Floorplanning, Power Grid Design, Placement, Routing, Physical Verification.- Must have experience on Analog Design Methodologies and sub-micron technology of 3 nm and other lower technology nodes.- Must have hands-on experience on Analog Design Suite from Cadence & Synopsys (... 

Looper Development Services Private Limited

Noida
7 days ago
 ...FinFET and/or nanosheet processes (5nm or newer). ● Experience in Layout design of library cells, datapaths, memories in deep sub-micron technologies. ● Knowledge of all aspects of Layout floorplanning and hierarchical assembly. ● Knowledge of Cadence Virtuoso and... 

Qualcomm Technologies, Inc

Bangalore
7 days ago
 ...circuits Expertise in design of RF/Analog integrated circuits required such as LNA, Mixer, RF VGAs, PA, VCO, PLL, Regulators, etc. in sub-micron CMOS technologies. Experience with MCU-based systems, functional safety, and automotive design are all beneficial. Cross... 

L&T Semiconductor Technologies

Bangalore
2 days ago
 ...CTS, Routing, STA, Power Integrity Analysis, Physical Verification. · Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. · Should have experience on programming in Tcl/Tk/Perl. · Must have hands-on... 

Wipro

Bangalore
24 days ago
 ...languages. - Experience in modifying STA constraints to check timing closure feasibility Have hands-on experience in latest sub-micron technologies below 10 nm • Hands –on experience in leading PnR tools Synopsys ICC/ICC2 Salary: Depending upon [Skill Sets & Current... 

ProConnxt

Hyderabad
29 days ago
 ...and physical verification. Exp with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues. Solid knowledge on physical design flow, Timing closure and physical verification. Knowledge of formal... 

Alp Consulting Ltd.

Bangalore
29 days ago
 ...Attributes Mandatory: circuit design fundamentals, device physics, basic understanding of layout and parasitic optimization, spicesub-micron design methodologies, Transmitters, Receivers, Clocking circuits, equalizers, serializers, de-serializers, Analog Front End... 

Synopsys Inc

Noida
29 days ago
 ...industry. The ideal candidate will have previous working experience at reputable manufacturers such as Intel, AMD, NVIDIA, Samsung, Hynix, Micron, or other key commodity manufacturers. If you have a passion for cutting-edge technology and a proven track record in sales management... 

Smith & Associates

Bangalore
5 days ago
 ...circuit .Should have basic understanding of layout and parasitic extraction .Comfortable with spice simulations and various sub-micron design methodologies .Familiarity with automation / Scripting language is desired Preferred Experience. Has a strong desire to... 
Noida
more than 2 months ago
 ...develop or enhance productivity tools Familiarity with Verification Flow   Preferred Qualifications In-depth knowledge of sub-micron technology is highly desired Strong project management skills Experience working with global design and cross functional teams... 

Murata America

Chennai
more than 2 months ago
 ..., current mirrors, regulators,…) Good knowledge on CMOS, FINFET technologies. Knowledge of CMOS Fabrication technology, deep sub-micron effects and its impact on layout. Knowledge on EMIR, ESD,LUP, Cross talk, Shielding and its impact on design. Hands on knowledge... 
Pune
more than 2 months ago
 ...involved in IC Layout development, with responsibility for analog/mixed-signal cell, block and chip-level custom layouts in deep sub-micron CMOS, SiGe and BiCMOS process technologies. You will quickly ramp on the existing flow, understand the challenges, and produce the work... 

Intel Corporation

Bangalore
3 days ago
 ...CTS, Routing, STA, Power Integrity Analysis, Physical Verification. · Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. · Should have experience on programming in Tcl/Tk/Perl. · Experience on Synopsys/... 

Wipro

Hyderabad
more than 2 months ago
 ...verification. · Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understanding deep sub-micron technology issues. · Solid knowledge of LP Design, DFT, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification,... 

Cadence Design Systems

Pune
more than 2 months ago
 ...CMOS circuit design fundamentals, device physics, basic understanding of layout and parasitic extraction, spice simulation, sub-micron design methodologies, PLL/DLL, Voltage Regulators, data converters, Equalizers, Impedance calibrators. Analog transistor level circuit... 
Noida
more than 2 months ago
 ...-Vt flow, power supply management etc.) ~ Circuit level comprehension of time critical paths in the design Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.) ~ Tcl/Perl scripting Willing to handle technical deliveries... 

Qualcomm Technologies, Inc

Bangalore
3 hours agonew
 ...platform infused with pre-trained defect libraries. Our proprietary model incorporates AI to detect manufacturing defects of less than 4 microns at 120 FPS. Our solution is deployable with existing cameras or basic camera equipment in open environments and can be operational... 

Lincode Labs Pvt. Ltd.

Bangalore
7 days ago
 ...RTL to GDSII, including development of timing constraints - is an expert with the implementation flows and methodologies for deep sub-micron designs - has experience in high performance digital design and CAD, high-speed design, low-power design, high speed clock design... 
Hyderabad
more than 2 months ago
 ...requirement for high speed data transfer is the need of the hour, as the fabrication and Datapath convergence is closely controlled by sub-micron limitations; There is always scope for improvements and enhancements that are required for successful data transfer with the required... 
Bangalore
more than 2 months ago
 ...requirement for high speed data transfer is the need of the hour, as the fabrication and Datapath convergence is closely controlled by sub-micron limitations There is always scope for improvements and enhancements that are required for successful data transfer with the required... 
Hyderabad
more than 2 months ago