...Greetings From Maneva!
Job Description
Job Title OpenText Info Archive
Location PAN India
Experience 7 12Years
Notice 45 Days
Job Requirements:
~10 years of extensive working experience with OpenText Info Archive version...
...Role : Info Archive Senior Consultant
Location : Bengaluru / Hyderabad
Shift time : 9 AM to 6 PM IST
Experience : 4 to 10 Years
CTC : 18 to 28 LPA
JD:
Resource will be working on Info Archive Products like Info Archive shell Submission Information Packages...
Required Skill Set
~ Highly proficient in SoC Architecture. Good prior experience (as a performance architect) in chipset peripherals & subsystems i.e. Audio, Video, Storage, Power, Cache, memory, Camera, CPU, DPU, VPU & Thermal etc.
~ Extensive Experience in Linux device...
...Job Overview: As a Frontend Technical Manager specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the front-end stages of integrated circuit development. This role requires a strong technical background in digital design, verification,...
...the rules of cutting-edge technology through relentless innovation to foster a vibrant culture of ingenuity, fuelling progress on every chip.
We have a presence in four prominent geographies i.e. US, Europe, Japan and India, with offices in Austin, Munich, London, Tokyo,...
...We are hiring PD full chip leads for Bangalore location.
KEY RESPONSIBILITIES:
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip Hierarchical planning, block planning, block level constraints, hierarchical...
...Job Overview: As a Backend Technical Manager specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the back-end stages of integrated circuit development. This role requires a strong technical background in physical design, a deep understanding...
At First Advantage (Nasdaq: FA), people are at the heart of everything we do. From our customers and partners to our greatest advantage — our team members. Operating with empathy and compassion, First Advantage fosters a global inclusive workforce devoted to the diverse voices...
...Job Description
Job Details: Job Description: Experience with owning the full chip/Block level and taping out multiple complex
SoCs. Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc...
...re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for... ...The Synopsys Information Security team is searching for a Senior Info Security Operations Engineer (Incident Response) who will be an integral...
...related tasks.
Experience and knowledge in scan insertion, memory BIST, Logic BIST, JTAG, and boundary scan logic features on the chips.
Knowledge of ATPG/Scan, coverage analysis, EDT compression etc., Memory BIST implementation and verification, Simulations
Implementation...
...Strong debugging and problem-solving skills. Experience with common embedded protocols/interfaces like I2C, SPI, USART, buses, bridge chips, FPGAs, hardware queues/FIFOs, interrupts, DMA, Experience in multi core, multi thread, IPC, system programming, GDB, kernel/user space...
...Collaborate in a small team & business stakeholders using your engineering background to get work done!
Learn data driven tools and help chip in to our ever-evolving metrics, alerting and decision-making platform.
Exert your independence and ability to learn unfamiliar...
...Job Description
Come and work in a worlds class security team to bring in industry defining solutions !
Architect System-on-chips which will transform next generation infrastructure products in the industry
Develop innovative platform, hardware, software level...
...checks and low power checks.
DFT insertion and ATPG analysis for optimal SAF, TDF coverage.
Provide support to SoC integration and chip level pre/post-silicon debug.
Skills & Experience
MTech/BTech in EE/CS with hardware engineering experience of 2-6 years....
...~ RC/C model selection understanding.
~ Abstraction expertise like Hyperscale/ILM/ETM.
~ RC Balancing and scaling analysis of full chip clock.
~ RC Balancing and scaling analysis of critical data paths.
~ Good automation skills in PERL, TCL and EDA tool-specific scripting...
...Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design
DFT LEAD REQUIREMENT -
Participate and drive SOC full Chip DFT feature and architecture definition
Responsible for DFT specification generation and review
Drive a team to implement SOC DFT...
...Chip level floorplanning, partitioning, timing budget generations, power planning, top PnR, CTS, block integration and ECO generation.
Hands on experience in ICC and primetime.
Block level implementation from netlist to GDS.
Handling timing closure of high frequency...
...systems, and risk management methodologies
Minimum of 2 Smart Card Manufacturing/ Personalization Bureau Auditing experience (Magstripe, Chip Card and Contactless Card) in Physical & Logical Security aspects
Hands on experience on identifying risks in card manufacturing...
...PHY, MAC, RF and board – with a sharp focus on solving the underlying problem.
d.Working with cross functional teams to ensure the chip meets all the 802.11 WLAN standard specifications and regulatory requirements Driving decarbonization and digitalization. Together....
...As an SoC Micro-Architect, you will play a key role in the design and development of complex ASICs and System-on-Chip architectures for various electronic devices. You will be responsible for defining the microarchitecture of the SoC, optimizing performance, power efficiency...
...either (System)Verilog or VHDL RTL coding and ASIC design methodology
Proven ability to optimize and develop design architecture from chip inception through to compliant netlist.
Proficiency in developing block and top-level timing constraints for STA and P&R signoff....
...These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important...
...edge SerDes design. As the lead of the micro-architectural definition and design implementation, the selected candidate will drive logic chip design achieving data of 16Gbs and above.
SoC Micro-Architect, you will play a key role in the design and development of complex...
...Strong debugging and problemsolving skills.
Experience with common embedded protocols/interfaces like
I2C SPI USART buses bridge chips FPGAs hardware queues/FIFOs interrupts DMA
Experience in multi core multi thread IPC system programming GDB kernel/user space...
...multi-cycle path handling
Hands-on experience with STA tools - Prime-time, Tempus
Have experience in driving timing convergence at Chip-level and Hard-Macro level
In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling...
...working knowledge of recent verification methodologies (UVM)
· Domain expertise in one or more of the following areas.
1. System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects
2. Verification of embedded CPUs such as ARM,...
...Familiarity with IoT (Internet of Things) and edge computing concepts.
Knowledge of containerization technologies (e.g., Docker).
Experience with board support package (BSP) development.
Understanding of hardware architectures and system-on-chip (SoC) concepts....
...Candidate having technical project execution experience is highly desired
Expertise in DFT technologies such as Scan Compression, On-chip DFT Fabric, ATPG, Diagnosis, MemoryBIST, LogicBIST, Boundary Scan
Previous experience and expertise in a customer facing role (...
...an experience in SoC Physical Design Skills - hands-on working experience with PnR, STA and PV tools. Delivering timing clean blocks/chip level flow methodologies that meet design targets. Education - B. Tech /M. Tech in Electronics Engineering. The individual must be self...