Average salary: Rs533,066 /yearly
More statsSearch Results: 1,192 vacancies
...information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
JR51161 Senior Engineer - ASIC Synthesis
. BS/MS in E&E or related field with 5+ years of experience.
. Proven hands-on experience constraint development for...
...performance, low-power, and area-efficient digital designs for ASICs and SoCs using industry-standard EDA tools.
Work closely with... ...Write and implement block level and top-level constraints for synthesis,perform timing closure and power analysis.
Develop and implement...
...4-8 years of experience in ASIC synthesis
Expertise in Synopsys/Cadence Synthesis tools : DC /FC/ Genus
Expertise with STA with Prime Time :
Good Experience in synthesis timing closure and interactions with DFT and PD.
Expertise in Low power flows for CLP, UPF (...
...for experienced SoC design engineers with SoC Logic Integration, Synthesis & STA closure experience to join our team in Bangalore India. The team is working on development of our next generation Control ASIC to production in 22nm technology. The ASIC will be a Mixed Signal...
...Job Area: Engineering Group, Engineering Group Hardware Engineering General Summary:
Qualcomm Chennai is looking for a STA and Synthesis Engineer who is passionate in to work with cross-functional engineering teams. In this position, the engineer will be involved in...
...of diverse perspectives.
AMD together we advance_
THE ROLE (ASIC Lead - Director):
As an Individual Contributor (IC) role you will... ...flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis DC/FC, ICC, and Physical design implementation/signoff tools....
...Greetings from TechMahindra!!!4 to 6 years of work experience in ASIC/IP Design.
Experience in Logic design / RTL design
Experience... ...development such as Lint and CDC are a must.
Experience in Synthesis / Understanding of timing concepts is a plus.
Good to have knowledge...
...logic design aspects ranging from RTL to timing/power convergence.
o Hands on experience in running Synopsys Fusion Compiler for Synthesis and Area and performance estimation
o Perform RTL Lint check, Equivalence checking, CDC checking and support Static Timing Analysis...
...Job Title: ASIC RTL Engineer Duration: Fulltime
Location: Bangalore
Description:
Experience in front end RTL design and front... ...Experience in post RTL checks — Lint, CDC, RDC
Experience in RTL synthesis and static timing analysis
Experience in working with...
...Title: STA/Synthesis Engineer Location: Bengaluru or Hyderabad
Description:
1. Performing Timing closure of partitions at SoC level
2. Providing placement feedback with respect to timing
3. Reduction of clock ID, by analyzing necessary tap points
4. Providing clock...
...organization.
Location: BANGALORE
Experience:5+Years
Notice Period: Immediate to 30 days only
Role: SYNTHESIS
Job Description
5-8 years of experience in ASIC Logical/Physical synthesis/STA
Expertise in Synopsys/Cadence Synthesis tools (Design Compiler/Genus...
...NVIDIA is seeking a passionate, highly motivated, and creative ASIC Design Engineer to design and implement PCI Express controllers for... ...understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up...
...multiple power domains using UPF/CPF.
Collaborate closely with ASIC architecture, design, and verification teams to triage and... ...verified SoC chip-level ASIC RTL, Gate Netlist, and FPGA RTL to the synthesis and implementation team.
Work on the setup and execution of Gate...
Our client is looking for an ASIC (RTL) Design Lead. (Not FPGA Design)
Please share only immediate joiner resumes . Job Location Can... ...integration
~ Lint, CDC
~ Constraint updation (IP to SoC level), Synthesis and timing analysis
~ PD Support
Please share your profile...
...and SoC level integration using Verilog/System Verilog.
* In depth knowledge on RTL quality checks (Lint, CDC).
* Knowledge of synthesis and low power is a plus.
* Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB).
* Good understanding of timing concepts...
...ASIC RTL Design Lead (ONLY IMMEDIATE JOINERS) Job Location : Bangalore, Hyderabad, Pune, Noida, Ahmedabad, Chennai
~12-15 years of experience... ...Processor subsystem integration
~ Lint, CDC
~ Constraint updation (IP to SoC level), Synthesis and timing analysis
~ PD Support...
...BIST, JTAG tools and flow.
Preferred qualifications:
Experience with a scripting language such as Perl.
Experience with Synthesis, Logic Testing, and ATPG.
Knowledge of design DFT techniques used for logic testing.
Ability to scale DFT, with a focus on minimal...
...communicate and advance faster than ever.
JR49460 Senior Engineer - ASIC Design
BS/MS in E&E or related field with 6+ years of... ...of IP and SoC design flows and methodologies (Lint, CDC, Synthesis/STA, Power)
Excellent problem-solving skills.
Team player with...
...Description
NVIDIA Clocks and Resets group is looking for a top ASIC engineer with extensive experience in high-speed logic design and... ...the way to Silicon bringup!
Get exposure to CDC, RDC, Lint, Synthesis, multi-power-domain designs and latest methodologies.
What we...
...for experienced Individual contributor for Physical design, using Synthesis -Automatic Placement and Route flow, from RTL to GDS , including... ...exposure to Synthesizable Verilog / System Verilog, RTL coding for ASIC designs and Simulation tools will be plus. Any scripting language...
