Average salary: Rs533,066 /yearly
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- ...you like connecting design intent with silicon reality, this role hits that sweet spot. ~5–9 years in ASIC design and implementation ~ Strong experience in Synthesis, STA, DFT, Lint, and CDC ~ Hands-on with timing constraints and closure ~ Experience with Tempus and...SuggestedFull time
- ...Job Requirements Job Title: STA / Synthesis - Technical Manager Job Type: Full-Time We are looking for a skilled STA / Synthesis -... ...related field Proven experience in STA and Synthesis for complex ASIC designs Strong knowledge of industry-standard EDA tools and...SuggestedFull time
Quest Global
Bangalore2 days ago - ...Timing constraint (Hierarchical, Flat) development and release for Synthesis/PD work o Timing constraint validation using various EDA tools... ...at full chip and/or sub system level is a plus . Knowledge of ASIC Back End flows and relevant Tools . Good automation skill...SuggestedFull time
Samsung R&D Institute India - Bangalore Private Limited
Bangalorea month ago Rs 4 - 9 lakhs p.a.
...optimization tasks. Staying updated with the latest advancements in ASIC design flow, VLSI, and CAD development to continually improve... ...4+ years of relevant experience. Hands-on experience with synthesis and place and route (P&R) tools. Proficiency with EDA tools such...SuggestedWorldwideSynopsys
Secunderabad3 days agoRs 14 - 19 lakhs p.a.
...multi-threaded and distributed code development. Familiarity with ASIC design flow and the EDA tools and methodologies used therein.... ...problem-solving skills. Desirable Skills: Work experience in Synthesis tools Work experience in EDA Experience in technically leading...SuggestedSynopsys
Noida3 days ago- ...Hardware Engineering General Summary Role Overview The NPU Synthesis Lead will be responsible for driving synthesis and timing closure... ...Required Skills Technical Expertise Strong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R. Proficiency in synthesis...Suggested
Qualcomm
Bangalore9 days ago - ...We are seeking a Principal Engineer – Implementation Lead to own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs... ...Engineering or Computer Science with 15+ years of experience in ASIC/SoC implementation Proven experience in mature-node...SuggestedFull timeHybrid workWork at officeRemote jobWorldwideFlexible hours2 days week
Renesas Electronics
Secunderabad2 days ago Rs 13.5 - 17.5 lakhs p.a.
...As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration team... ...timing. ~ Coordinated cross-functional efforts across design, synthesis, P&R, and verification teams to ensure timing signoff. ~ Owned...SuggestedFull timeAdvanced Micro Devices (AMD)
Bangalore2 days ago- Hiring : ASIC Engineering Director : Job Location : HyderabadExperience : 20+Years Our game-changing AI solutions revolutionize what people... ..., IP/Sub- systems/SOC/chiplets design/integration, RTL coding, Synthesis, CDC, timing, power analysis, system/IP verification, Silicon...Suggested
- ...Posted 11.26.2025 Alternate Job Titles: ~ Principal Engineer - ASIC Digital Design IP Development (Ethernet/UALink Protocols) We... ...in ASIC design, including control path-oriented architectures, synthesis flows, and verification methodologies. As a technical leader,...SuggestedRemote jobWorldwide
Rs 4 - 8 lakhs p.a.
...Specifications Hands on experience with Synthesizable Verilog/ System Verilog RTL coding for ASIC designs and Simulation tools Lint, CDC, Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background Experience with high...SuggestedSynopsys
Pune3 days ago- ...RTL design expert with a proven track record in leading complex ASIC digital subsystems from concept to silicon. Thriving on technical... ...silicon. Solid understanding of the ASIC design flow, including synthesis, timing analysis, and physical implementation. Who You Are:...Suggested
Synopsys Inc
Bangalore23 days ago Rs 6.5 - 10 lakhs p.a.
...flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical... ...years of professional experience in physical design, preferably ASIC designs. ~ Experience in automated synthesis and timing driven...SuggestedAdvanced Micro Devices (AMD)
Bangalore2 days ago- ...languages, such as Verilog or SystemVerilog. ~3 years of experience in ASIC design flows and methodologies, IP integration (e.g., subsystems,... ..., IO's and Analog IP) and RTL design. ~ Experience with logic synthesis techniques to optimize RTL code, performance and power, as well...SuggestedWorldwide
Google
Bangalore23 days ago - ...ASIC Design Engineer We are seeking a skilled ASIC Design Engineer with a solid background in digital design , RTL coding , and... ..., memory controllers , and high-speed interfaces. Synthesis & Optimization: Perform logic synthesis , timing analysis ,...Suggested
ACL Digital
Bangalore2 days ago - ...Job Title: Principal ASIC Design Engineer – Die-to-Die Protocols Location: Noida/Pune We Are: At Synopsys, we drive the innovations... ...flows and have mastered tools including Verilog/SystemVerilog, synthesis, CDC analysis, and static timing. Your background includes the...Worldwide
Synopsys Inc
Noida22 days ago Rs 3 - 10 lakhs p.a.
...external stakeholders to align on project goals and deliverables. What You ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design...Synopsys
Noida3 days ago- ...micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other... ...tools, debug tools like Debussy, GDB). ~ Deep understanding of ASIC design flow including RTL design, verification, logic synthesis,...
Nvidia
Bangalore1 day ago - Description :- Expertise in ASIC physical design- Expertise in full-chip implementation, bump placement, IP integration, and timing-driven PnR.- Expertise in clock tree synthesis, power/clock gating, scan stitching, and design optimization.- Expertise in floor planning, methodology...Full time
- ...different designs and technology nodes. Who You Are You are an ASIC engineer with 6+ years of related work experience with a broad... ...Floor planning and P&R tools: Cadence Innovus & Synopsys FC Synthesis Tools: Synopsys DC/FC Static Timing verification: Primetime-DMSA...
Cisco DevNet
Bangalore2 days ago Rs 6 - 9 lakhs p.a.
...simulations. Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. Participate in synthesis, timing/power estimation... ...SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology. ~ Experience with a coding language like Python or...Google Inc
Bangalore7 days ago- Sr. Staff Engineer – ASIC Physical Design We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our... ...cores and/or SOCs development. You have a solid understanding of Synthesis, Place & Route, and ASIC design flows. Your technical expertise...
Synopsys Inc
Secunderabada month ago - ...reviewing and providing guidance in floorplanning, power analysis, synthesis and timing signoff. Work with the verification team on pre-... ...with System Verilog assertions Well-versed in all stages of the ASIC design flow (including specification, architecture and design...Permanent employmentFull time
Marvell Technology
Bangalorea month ago Rs 4 - 9 lakhs p.a.
...Design GPU or CPU cores and ASICs for high-volume multimedia and graphics applications. Implement and verify RTL using Verilog/VHDL for deep sub-micron CMOS technology. Conduct synthesis, static timing analysis, low power design, and design-for-test (DFT). Develop...Qualcomm
Bangalore7 days agoRs 3 - 7.5 lakhs p.a.
...design, multi-power domains with clocking, and SoCs with silicon. ~ Proficiency in Verilog or SystemVerilog language. ~ Experience with ASIC design methodologies for front quality checks like Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, and Low Power Estimation....Google Inc
Bangalore7 days agoRs 3 - 15 lakhs p.a.
...through successful project deliveries. What You ll Need: Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding. Proficiency in writing synthesis constraints and basics of STA. Knowledge of Lint/CDC/RDC and RTL2GDSII flow....Full timeSynopsys
Noida3 days ago- ...technological innovation. You Are: An experienced and passionate ASIC Digital Design Engineer who thrives in dynamic and collaborative... ...and IP development flow, including RTL design, lint, CDC,RDC,synthesis andSTA. Experience with power analysis and RTL level power...Full time
Synopsys Inc
Bangalore23 days ago Rs 3 - 10.5 lakhs p.a.
...Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line. Performing synthesis, physical design, verification, design for test, and ATPG. Contributing as a senior member of a design team or as a project design engineer working...Synopsys
Secunderabad3 days agoRs 2 - 5 lakhs p.a.
...RTL) quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, Unified Power Format (UPF) checks. Participate in synthesis,... ...equivalent practical experience. Experience with digital design in ASIC. Experience with RTL design using Verilog/System Verilog and...Google Inc
Bangalore7 days agoRs 5 - 8 lakhs p.a.
...Key Responsibilities: Collaborate on ASIC backend design activities including synthesis, place-and-route, timing analysis, and physical verification. Develop and optimize design flows using EDA tools (e.g., Synopsys, Cadence, Mentor). Perform static timing analysis...Teamware Solutions
Secunderabad23 days ago
