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  •  ...As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration...  ...Design teams, and product engineers to achieve first pass silicon success...  ...and ensure a quality handoff for STA checks Requires a mix of SDC... 
    Suggested
    Full time
    Bangalore
    25 days ago
  • Description :- Expertise in ASIC PD- Expertise in digital physical design- Expertise in working with 3nm & 5nm technology nodes- Expertise in EDA synthesis, APR, STA tools and methodologies- Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus- Working... 
    Suggested
    Bangalore
    22 days ago
  •  ...we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson System...  ...end-customers. At our state-of-the-art design centers, we don't just follow industry...  ...specifications. Work closely with verification engineers to review and refine verification plans.... 
    Suggested
    Full time
    Worldwide
    Bangalore
    2 days ago
  • Description : STA Engineer (Static Timing Analysis) VLSILocation : Bangalore, IndiaExperience :...  ...Engineer with a strong background in VLSI design and timing closure. The ideal candidate...  ...off quality results for complex SoCs and ASICs.Key Responsibilities :- Perform Static Timing... 
    Suggested
    Full time

    GiGa-Ops Global

    Bangalore
    5 days ago
  •  ...significant role in it. This is what you are responsible for Physical Design of complex data path and control blocks Develop new techniques...  ...experience with Synthesis, Automatics Place-and-route, Full Chip STA, IO Planning, Full Chip Floorplan, Power Mesh creation, Bump... 
    Suggested
    Full time
    Secunderabad
    3 days ago
  •  ...we pioneer the IPs that power the digital ASICs of tomorrow's mobile standards. Ericsson...  ...their end-customers. At our state-of-the-art design centers, we don't just follow industry...  ...'s degree in electrical or computer engineering. ~10+ years industry experience in ASIC... 
    Suggested
    Full time
    Worldwide
    Bangalore
    2 days ago
  •  ...driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the...  ...Are: You are a passionate and detail-oriented engineer with a deep understanding of Static Timing Analysis (STA). You thrive in a collaborative environment, working... 
    Suggested
    Flexible hours
    Noida
    1 day ago
  •  ...Alternate Job Titles: ASIC Physical Design Engineer Place & Route Engineer Sr. Physical Design Specialist We Are: At Synopsys, we drive...  ...thorough physical verification (DRC/LVS), timing analysis (STA), and addressing design closure challenges across advanced technology... 
    Suggested
    Bangalore
    1 day ago
  •  ...: [HIDDEN TEXT] We are recruiting for below roles # ASIC Physical Design Principal Engineer RTL2GDS : 15 - 25 Years # Senior Technical Architect -...  ...signoff closure, and flow correlation across synthesis, STA, and physical domains. Work Experience Skills &... 
    Suggested
    Full time
    Bangalore
    1 day ago
  • Job Titles: ~ Senior Staff ASIC Verification Engineer- Pune Location We Are: At Synopsys, we drive the innovations that shape the way we...  ...from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of... 
    Suggested
    Shift work
    Pune
    1 day ago
  •  ...chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation; Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros... 
    Suggested
    Full time
    Bangalore
    26 days ago
  •  ...Job Description Your Role As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will collaborate closely with cross-functional teams including physical design, logic design, and architecture to ensure timing... 
    Suggested
    Full time
    Shift work
    Bangalore
    6 days ago
  •  ...Summary: The Digital Physical Design Engineer is responsible for a physical implementation of IP Subsystem or IC design. Job qualification...  ...flows. Should have worked on Genus flows. Should be good in STA flow setup and STA flows. Should have worked in Tempus flows.... 
    Suggested
    Full time

    NXP Semiconductors

    Bangalore
    12 days ago
  •  ...innovation we are pursuing! Position Description: ~ Design and d evelop RTL in Central Engineering team for products which includ es blocks such as...  ...microarchitecture Experience ~ Working knowledge of Synthesis STA Lint & CDC ~ Experience in high speed FPGA RTL... 
    Suggested
    Full time
    Immediate start

    Micron

    Bangalore
    a month ago
  •  ...manner) Candidate will be responsible for RTL design for integration of IO pads into SoC,...  ...this task if you have: Must have worked in ASIC Design flow, with ASIC experience of upto 5...  ..., Timing constraints and debugging STA reports. Strong mindset towards automation... 
    Suggested
    Bangalore
    1 day ago
  •  ...Alternate Job Titles: ~ Senior RTL Design Lead We Are: At Synopsys, we drive the...  ...a proven track record in leading complex ASIC digital subsystems from concept to silicon...  ...architectural level. Mentoring junior engineers and participating in technical reviews to... 
    Bangalore
    1 day ago
  •  ...cars to learning machines. We lead in chip design, verification, and IP integration,...  ...innovation. You Are: You are a passionate engineer who thrives in a collaborative and challenging...  .... You possess deep expertise in ASIC physical design, particularly in implementing... 
    Local area
    Bangalore
    1 day ago
  •  ...resolving timing issues, and ensuring design closure for performance, power...  ...and closing timing for ASIC designs by creating and...  ...Master's degree in Electronics Engineering, or a related field. Experience...  ...in industry-standard SDC and STA (Static Timing Analysis) tools... 
    Full time
    Hybrid work
    Work at office
    Bangalore
    3 days ago
  •  ...Perform hands-on physical design and physical verification tasks...  ...nodes. Manage project-specific ASIC development flow setup and...  ...Experience with Cadence PnR/STA tools and Calibre; good scripting...  ...Tech /M. Tech in Electronics Engineering. ' We have a flexible work... 
    Full time
    Work at office
    Flexible hours
    Bangalore
    3 days ago
  •  ...and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact As a Digital IC Design Senior Staff Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering... 
    Permanent employment
    Full time
    Bangalore
    2 days ago
  • As a part of Arm's Solutions Engineering group we like to think we are not just crafting...  ..., but we are defining future chip design techniques. Not only do we improve...  ...~7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured... 
    Hybrid work
    Work at office
    Local area
    Noida
    1 day ago
  •  ...signoff team part of The Central Engineering PD group at Marvell, Bangalore...  ...implementation all custom ASICs for all the OEM's. We are looking...  ...having experience in STA using industry standard tools....  ...process technology. Work with design teams across various disciplinessuch... 
    Permanent employment
    Full time
    Bangalore
    2 days ago
  •  ...work at Microchip because we help design the technology that runs the...  ...Description: As a Design Engineer in the FPGA Business Unit, you...  ...Experience: 8 to 12 years in ASIC/FPGA design, with at least 5 years...  ...Good understanding of synthesis, STA, timing closure, and ECOs... 
    Full time
    Secunderabad
    3 days ago
  •  ...Job Designation: ASIC Physical Design Engineer Brief Role Should have 5 years of physical design experience, with recent successful tapeouts in deep submicron technologies (45nm and below). Strong knowledge of Full chip floor planning, partitioning, and Detailed PD... 
    Full time
    Bangalore
    3 days ago
  • Principal Verification Engineer We Are: At Synopsys, we drive the innovations that shape...  ...to learning machines. We lead in chip design, verification, and IP integration, empowering...  ...You are an experienced and innovative ASIC Digital Design Principal Engineer with a passion... 
    Bangalore
    1 day ago
  •  ...ASIC Verification Engineer Experience: 4+ Years Responsibilities: You will be exposed to the latest verification methodologies like...  ...and Gate level simulation. (30%) Work closely with logic designers to resolve bugs and software developers to assist in software... 
    Bangalore
    3 days ago
  • Job Title : Senior Verification Engineer (hardware)We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects.About... 

    5G-AI

    Hyderabad
    8 days ago
  •  ...Job Title: ~ IP Design Technical Lead/ Staff ASIC RTL Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines... 
    Bangalore
    1 day ago
  • Job Title: ~ Principal ASIC Digital Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design... 
    Worldwide
    Bangalore
    1 day ago
  •  ...skilled and enthusiastic Digital Physical Design Engineer (G2) to contribute to the physical...  ...tree synthesis, and static timing analysis (STA). * Perform physical verification (DRC,...  ...digital physical design of complex SoCs or ASICs. * Proficiency with industry-standard EDA... 
    Pune
    11 days ago