Search Results: 16 vacancies
...Experience with Cadence layout tools ( Innovus, Tempus , etc..)
Hands-on work experience in Physical verification closure (DRC/LVS/Antenna) with the Caliber tool
Experience in closing all the IR issues within the block based on feedback
Should be strong in...
...critical analog, mixed-signal, custom digital block and full chip level integration support.
Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate...
...practice with 2years' experience in programming EDA software.
Strong knowledge required on layout matching technics, Shielding, EMIR, Antenna
Understanding capability to solve physical verification: DRC/LVS/ERC
Understanding of Linux and common scripting languages (...
...critical analog, mixed-signal, custom digital block and full chip level integration support.
Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
Responsible for on-time delivery of block-level layouts with acceptable quality.
Demonstrate...
.../or any other physical verification ) tool.
Hands-on Experience in Physical Verification Knowledge on DRC, ERC, LVS, DPT, Antenna, DFM, PERC checks and fixing.
Experience in tape-outs in 5nm and below technologies.
Responsibilities will also include working...
...6 years of experience in RF design and development
~ Strong knowledge of RF circuit design and simulation tools
~ Experience in antenna design and optimization
~ Proficient in PCB design
~ Hands-on experience in Radio Frequency (RF) engineering
~ Knowledge of microwave...
...critical analog, mixed-signal, custom digital block, and full chip level integration support.
.Perform layout verification like LVS/DRC/Antenna, quality check and support documentation.
.Responsible for on-time delivery of block-level layouts with acceptable quality.
....
...subsystem-level flat and hierarchical designs.Physical verification tasks include creating ICV setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database.
What You'll Need...
...in Altium Design.- High Speed Design like DDR4, HDMI, MIPI.- Past Wearable design experience.- Simulation Tools Hardware/ Software.- RF Antenna Design with maximum efficiency- Flex PCB and Rigid-Flex PCB Design along with Mechatronic design considerations. (ref:hirist.tech)
...analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating...
...with AMS-RF physical implementation flow from floorplan to GDS including: Floorplan, placement, routing and verification (LVS, DRC and Antenna checks)
• Experience with both advanced nodes (FinFET Technologies, 5nm and 16nm) and mature nodes (28nm, 40nm and above)
Kindly...
.../16/32bit micro controllers or processors. TIs MSPxxx series, NXP, Si-Lab devices, Analog devices, Qualcomm, etc.
Knowledge of RF/Antennas, design and testing of RF signal chain (transmit and receive) design.
Experience in design for EMI-EMC compliance, resolution of EMI...
...like Totem/VoltusXFA/XA is preferable.
~ Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna Calibre/ICV rule deck issues is plus.
~ Good understanding of advanced CMOS process manufacturing and layout design rules, EMIR, RC...
...Ability to understand design constrains and implement high quality layouts.
Strong debug and problem solving skills for LVS,DRC,Antenna and EM/IR.
Multiple tape out support experience will be an added advantage.
Excellent written and oral communication skills required...
...motivated with passion, detail oriented, systematic and methodical approach in IC layout design
.Perform layout verification like LVS/DRC/Antenna, quality check and documentation.
.Responsible for on-time delivery of block-level layouts with acceptable quality.
....
...verification collaterals using SVRF.
Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna and rule deck issues.
Good understanding of basic CMOS process manufacturing and layout design rules.
Working knowledge of Linux...
