mts dft design engineer Job Description Template
Our company is looking for a mts dft design engineer to join our team.
Responsibilities:
- ATPG patterns verification with gate level simulation;
- Post silicon support to ensure successful bringup and enhance yield learning;
- Test coverage and test cost reduction analysis;
- Memory BIST logic generation, implementation and verification;
- Implementation and verification of DFT architecture and features;
- Scan/Jtag/boundary scan insertion and ATPG pattern generation.
Requirements:
- Minimum 8 years working experience in ASIC DFT area;
- Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design;
- Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX;
- Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, ? etc);
- Excellent oral, written and interpersonal communication skills.