Principal Logic Design Engineer Job Description Template
Our company is looking for a Principal Logic Design Engineer to join our team.
Responsibilities:
- Support Customer integration activities;
- Drive the methodology on mixed signal IP flows on simulations, timing closure;
- Generating soft-macros (RTL) to be used in test-chip/product designs;
- Be a technical digital design lead for the PHY IP’s;
- Define or participate in micro-architecture definition and drive for power, performance and area (PPA) targets/enhancements;
- Own the design and methodology for execution on multiple IP’s on multiple technology nodes;
- Setup and analysis of lint, synthesis, timing closure and DFT reports;
- Develop micro-architecture and RTL design for digital components for memory and serdes PHY IPs.
Requirements:
- Experience in leading projects to deliver high-speed, high-performance IP design over advance technology nodes;
- Hands on experience on Lint/CDC, SDC ownership and qualification, Timing ECO iterations, debugging in mixed-signal simulation environment, etc;
- Electrical/Electronic Engineering with at least 8 to 12 years of experience in Logic design, Micro architecture definition, RTL design and STA;
- Experience with synthesis flow, hands on timing closure, ECO iterations;
- Experience coding within Verilog and/or System Verilog along with scripting languages such as Perl, Tcl, or Python;
- Knowledge of memory (DDRx/HBM/GDDRx) , serdes technology such as – PCI Express, Ethernet, USB is a plus;
- Experience in leading both IP design and TestChip/SoC integration;
- Experience working with multiple clock domains, high speed designs;
- Driving design flows and overall methodology;
- Understanding of the mixed signal IP flow with modelling and simulation;
- Experience in cross interaction with verification, DFT and physical design teams.