DFT Engineer Job Description Template
Our company is looking for a DFT Engineer to join our team.
Responsibilities:
- Post silicon support to ensure successful bringup and enhance yield learning;
- ATPG patterns verification with gate level simulation;
- Scan/Jtag/boundary scan insertion and ATPG pattern generation;
- Test coverage and test cost reduction analysis;
- Implementation and verification of DFT architecture and features;
- Memory BIST logic generation, implementation and verification.
Requirements:
- DFT logic integration and verification;
- Minimum 8 years working experience in ASIC DFT area;
- Gate Level DFT verification with and without timing;
- Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX;
- Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST, ? etc);
- Experience with VCS simulation tool, Perl/Shell scripting and Verilog RTL design;
- Pattern generation, verification and delivery to ATE team;
- Experience on improving coverage;
- Excellent oral, written and interpersonal communication skills;
- Post silicon debug and support on failing patterns;
- Good experience on EDA tools of reputed vendor like Mentor, Synopsis. LBIST experience is plus;
- DFT mode STA and timing closure support.