ASIC Physical Design and Synthesis/STA/DFT Senior/Lead/Staff

Company Description Appose is an innovative company dedicated to pushing the boundaries of semiconductor technology. Located in Bengaluru, we are focused on designing cutting-edge and innovative solutions for our customers. As a rapidly growing team, we prioritize a collaborative and forward-thinking environment. Join us to contribute to pioneering developments in the semiconductor space. Role Description This is a full-time, on-site role based in Bengaluru, for an ASIC Physical Design and Synthesis/STA/DFT Senior/Lead/Staff professional. The role involves leading and executing key tasks in physical design, design-for-testability (DFT), and Synthesis/static timing analysis (STA). You will be responsible for DFT architecture definition, flow setup, and driving design implementation from RTL to GDSII. Collaboration with cross-functional teams to meet performance, power, and area goals is a core part of this role. Qualifications Expertise in Cadence and Synopsys tools for ASIC physical design, Synthesis, DFT and STA Research capability to analyze and solve problems, and to contribute to technology development Strong understanding of complex high speed and low power design synthesis and implementation. Experience in static timing analysis (STA) and design-for-testability (DFT) techniques Proven ability to work in a fast-paced, multidisciplinary team Strong communication skills to effectively collaborate with different teams Minimum 3 years experience in the mentioned skills Relevant degree in Electrical Engineering, Computer Engineering, or a related field; advanced degrees are a plus