Lead DFT Engineer - MBIST/SoC

About the Role : We are looking for a Lead DFT Engineer to drive Design-for-Test implementation for complex SoCs across advanced technology nodes. You will own DFT architecture, implementation, and sign-off with a strong focus on Scan Insertion, MBIST, and ATPG, enabling high-quality silicon with optimal test coverage.What You'll Do : - Define and implement DFT architecture for complex SoCs and IPs.- Drive Scan Insertion, scan compression, scan stitching, and scan verification.- Develop and integrate MBIST solutions for embedded memories and memory repair flows.- Generate and optimize ATPG patterns for stuck-at, transition, and advanced fault models.- Perform DFT verification, coverage analysis, pattern validation, and debug.- Collaborate with RTL, Physical Design, STA, and Test Engineering teams to achieve DFT closure.- Drive DFT sign-off, improve test coverage, and optimize test time and silicon quality.- Develop automation scripts to improve DFT productivity and flow efficiency.What We're Looking For : - 10 - 12 years of hands-on experience in Design for Test (DFT).- Strong expertise in Scan Insertion, scan compression, and scan architecture.- Deep experience with MBIST implementation, integration, and verification.- Strong knowledge of ATPG generation, fault simulation, and coverage optimization.- Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, or equivalent.- Understanding of JTAG/IEEE 1149.1, boundary scan, and IEEE 1500 standards.- Experience with DFT validation, gate-level simulation, and scan debug.- Proficiency in TCL, Python, or Perl scripting for flow automation.- Excellent debugging, analytical, and cross-functional collaboration skills. (ref:hirist.tech)