Staff Engineer, Design Verification

Responsibilities:

• Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
• Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
• Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
• Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
• Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.
• Ensure IP deliverables meet quality, schedule, and reusability expectations for SoC integration.

Qualifications

• Bachelor’s or Master’s degree in electronics Engineering
• 5-12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.
• Strong expertise in UVM‑based testbench architecture and development
• Proven experience in metric‑driven verification, including functional and code coverage closure
• Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices
• Experience with directed and constrained‑random verification methodologies
• Experience debugging complex design issues in simulation, emulation, and post‑silicon environments
• Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting
• Strong analytical, problem‑solving, and communication skills

Preferred/Plus

Qualifications

• Hands‑on experience using AI/ML‑based verification tools for:
  • Coverage gap analysis
  • Test stimulus optimization
  • Regression triage and coverage acceleration
• Scripting expertise in Python, Perl, or TCL for automation and analytics
• Exposure to formal verification and hybrid formal‑simulation flows
• Familiarity with high‑speed or complex IPs, such as:
  • H.264
  • Security, debug, or safety‑crititical

Additional Information

Job Description

Renesas has a growing presence in India with HC approaching 1000+ and significant presence with active government and university collaboration as well as OSAT footprint (JV with CG India). With the growing importance of India as a market (Growing semiconductor market and government goals / mandates of localization needs) and talent hub, our division’s (India for India) mission is to grow India market. We aspire to create products (SoCs, Software, Power and Analog chips etc) which serve needs for local market. Renesas is a leading electronics supplier globally, and this is a unique opportunity to directly influence the future products which will be offered to our customers in a new, fast growing and large Indian market with specific needs and applications.

We are seeking a highly experienced IP Design Verification Engineer to join the Verification R&D team at Renesas. In this role, you will be a part of team responsible for SOC verification, ensuring first‑pass silicon success through building verification environment from scratch using best in class methodologies, metric‑driven verification, and intelligent coverage convergence using AI tools.

You will play a key technical role in defining verification strategies, architecting testbenches, defining Test Plans tracing Requirements, driving coverage closure using advanced automation and AI‑assisted techniques, and collaborating closely with Architecture, RTL, chip top, and Validation teams to deliver high‑quality, reusable IPs for next‑generation microcontrollers and microprocessors.

Responsibilities:

• Be a part of end‑to‑end verification execution for SOC owning complex digital IP’s and subsystems from specification to sign‑off
• Define and drive IP‑level verification strategies, including test plans, coverage models, and closure criteria
• Develop scalable, reusable UVM‑based verification environments for IP and subsystem verification
• Lead functional, code, assertion, and cross‑coverage closure, ensuring high‑quality sign‑off with clear metrics
• Apply AI/ML‑assisted verification techniques to accelerate coverage convergence, identify stimulus gaps, and optimize regression efficiency
• Drive constraint random and directed test methodologies for thorough protocol, corner‑case, and stress verification
• Collaborate with RTL, Architecture, Emulation, and SoC Verification teams to ensure seamless IP integration
• Review IP specifications and work with architects to translate requirements into robust verification plans and checkers
• Develop and deploy advanced checkers, scoreboards, assertions (SVA), and protocol monitors
• Work with EDA vendors to evaluate and adopt next‑generation verification, coverage, and analytics tools
• Mentor junior engineers and promote best‑in‑class verification practices and continuous improvement
• Support Gate‑Level Simulation (GLS), low‑power verification, and post‑silicon debug when required.

Qualifications

• Bachelor’s or Master’s degree in electronics Engineering
• 5-12 years of experience in SoC Verification domains and have working knowledge of industry standard EDA toolkits.
• Strong expertise in UVM‑based testbench architecture and development
• Proven experience in metric‑driven verification, including functional and code coverage closure
• Deep understanding of SystemVerilog, UVM, assertions (SVA), and verification best practices
• Experience with directed and constrained‑random verification methodologies
• Experience debugging complex design issues in simulation, emulation, and post‑silicon environments
• Proficiency in Verilog/SystemVerilog, with working knowledge of C/C++, Shell scripting
• Strong analytical, problem‑solving, and communication skills

Preferred/Plus

Qualifications

• Hands‑on experience using AI/ML‑based verification tools for:
  • Coverage gap analysis
  • Test stimulus optimization
  • Regression triage and coverage acceleration
• Scripting expertise in Python, Perl, or TCL for automation and analytics
• Exposure to formal verification and hybrid formal‑simulation flows
• Familiarity with high‑speed or complex IPs, such as:
  • H.264
  • Security, debug, or safety‑crititical

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.

With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’

At Renesas, you can: 

• Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.

• Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. 

• Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.

Are you ready to own your success and make your mark?

Join Renesas. Let’s Shape the Future together.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our  Diversity & Inclusion Statement .