Senior Lead Design Engineer

Job Opportunity: Seeking highly motivated energetic team-oriented Individual Contributor willing to go deeper into logic design and take the challenge of architecting and developing C omp lex IPs / Subsystems using the latest advanced Design flow methodologies and efficient techniques.

The person would be working closely with experienced and motivated team of global s ystems experts SoC Design functions to address the design/architectural challenges in the context of the complex IP Subsystem and overall System level designs towards providing a complete solution with end to end design flow from High L evel Specifications to actual design Implementation .

Key Responsibilities

• Architect and Design complex IP and Subsystems across a range of protocols for Auto motive Self Driving Vehicles ( ADAS) both Vision and Radar In- Vehicle networks Gateway S ystems Fail Safe Subsystems (ASIL-D) etc.

• Own and Lead IP / Subsystem from Concept till IP Design and Development achieving final design performance in integrated syst em within aggressive market driven schedules.

• Ensure quality adherence during all stages of the IP development cycle and carry out a thorough an alysis of existing processes recommend and implement the process improvements to ensure Zero Defect designs.

• Ability to work well as part of a team of global and local experts to influence and build technological innovations.

Key Skills

• Self starter with 7-13 years of experience to Architect and Design complex IP design / Sub-system with minimal supervision .

• Custom Processor Designs with key DSP functions like those needed for Vision and R adar processing .

• Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe USB & MIPI CSI / DSI .

• Understanding of key External Memory interface protocols including DDR4 / LPDDR4 QuadSPI Flash interfaces.

• Experience in microcontroller architecture Cache protocols like AHB/AMBA AXI.

• Experience in automotive protocols like LIN CAN Flex ray would be advantageous .

• E xtensive hands on knowledge of HDLs (Verilog/ VHDL) Scripting languages (Perl Tcl ) C/C for hardware modeling .

• Understanding of end to end IP development flow inc l uding complex CDC RDC constructs IP Synthesis DFT ATPG coverage.

• Work on Testbench and Testplan development closely with the verification team. Addressing of Testability aspects of the IP / Subsystem along with functional requirements would be an advantage.

• Hands on work on pre silicon validation using FPGA / Emulation Board would be a significant added advantage.

Key Soft Skills

• Proficient skills in both written and verbal communication . Can articulate well .

• Has a sense of Ownership and engages everyone with Trust and Respect .

• Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite .

Required Experience:

Senior IC