Tech Lead ASIC Design Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at .

Job Description: Lead Digital Design Engineer

Location: Bengaluru, India (Hybrid)

About Astera Labs

Astera Labs is a global leader in purpose-built semiconductor connectivity solutions for AI and cloud infrastructure. Our intelligent connectivity platform enables hyperscalers and system OEMs to maximize the performance and scalability of accelerated computing through industry-leading technologies such as Compute Express Link (CXL), PCI Express (PCIe), and Ethernet.

As AI and cloud workloads continue to evolve, Astera Labs is developing innovative silicon solutions that enable the next generation of high-performance computing. We are looking for a talented Lead Digital Design Engineer to join our Silicon Engineering team and contribute to the development of cutting-edge connectivity products.

Position Summary

As a Lead Digital Design Engineer , you will be responsible for the design and implementation of complex digital IPs and SoC subsystems for next-generation AI infrastructure products. You will drive RTL development from architecture through implementation, collaborate closely with cross-functional teams, and provide technical leadership to ensure high-quality, first-pass silicon.

This role requires strong expertise in RTL design, SoC integration, and high-speed interfaces, along with the ability to mentor engineers and lead technical execution.

Key Responsibilities

• Lead the architecture, microarchitecture, RTL design, and implementation of complex digital IPs and SoC subsystems for high-performance connectivity products.
• Drive end-to-end ownership of design modules from specification through RTL development, integration, and silicon bring-up.
• Design high-quality, synthesizable RTL using Verilog/System Verilog, ensuring optimal performance, power, area (PPA), and scalability.
• Develop complex data paths, control logic, finite state machines, arbitration mechanisms, and protocol engines.
• Design and implement solutions for high-speed interfaces and protocols, including CXL, PCIe, Ethernet, and AXI-based interconnects.
• Collaborate with Architecture teams to define microarchitecture and review functional specifications.
• Partner closely with Design Verification teams to develop verification strategies, debug design issues, and achieve functional closure.
• Work with Physical Design teams to resolve timing, power, congestion, and implementation challenges through RTL optimization.
• Support synthesis, lint, CDC/RDC, STA, DFT, and design sign-off activities.
• Participate in design reviews and ensure compliance with RTL coding guidelines and design best practices.
• Drive debug and resolution of RTL, integration, and post-silicon issues in collaboration with firmware, validation, and system engineering teams.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 6–12 years of experience in digital design for complex semiconductor products.
• Strong expertise in Verilog/System Verilog RTL design.
• Experience with complete ASIC design cycles from microarchitecture through RTL implementation and silicon bring-up.
• Strong understanding of digital design fundamentals, computer architecture, and SoC integration.
• Experience with synthesis, lint, CDC/RDC, STA, and RTL sign-off methodologies.
• Excellent debugging and analytical skills.

Preferred Technical Skills

Experience in one or more of the following:

• Compute Express Link (CXL)
• PCI Express (PCIe)
• Ethernet MAC/PCS
• High-speed networking or connectivity IP
• AXI-based SoC architecture
• DMA engines
• Packet processing pipelines
• Cache coherency protocols
• Memory controllers
• High-speed interconnects

Tools & Methodologies

• Verilog/System Verilog
• Synopsys Design Compiler
• Cadence Genus
• SpyGlass (Lint/CDC/RDC)
• Static Timing Analysis (STA)
• Git or other version control systems
• Python, Tcl, Perl, or Shell scripting

Preferred Experience

• Experience designing connectivity, networking, storage, or AI accelerator silicon.
• Proven track record of delivering successful ASIC or SoC tape-outs.
• Familiarity with high-speed protocols and data center technologies.
• Experience working in cross-functional global engineering teams.
• Exposure to low-power design methodologies and Design for Test (DFT) is a plus.

Why Join Astera Labs?

Astera Labs is redefining connectivity for AI and cloud infrastructure. As a Lead Digital Design Engineer, you'll work on industry-leading technologies that power next-generation data centers and accelerated computing platforms. You'll collaborate with world-class engineers, solve complex design challenges, and play a key role in delivering innovative semiconductor solutions that shape the future of AI.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.