RTL Design Engineer

The ideal candidate will develop high-quality RTL, drive IP/subsystem integration, and ensure design readiness through rigorous quality checks including Lint, CDC, RDC, synthesis, and handoff validation.

Responsibilities

Own RTL development from architecture interpretation through design handoff, including IP integration, clock/reset handling, address mapping, and configuration.

Perform detailed RTL reviews and quality assessments, identifying and driving closure of functional, structural, and methodology issues.

Analyze and resolve Lint, CDC/RDC, X-propagation, synthesis, and structural violations, collaborating with architecture, design, and verification teams.

Ensure RTL handoff readiness through clean signoffs, protocol compliance, register-spec alignment, and clock/reset architecture validation.

Build and enhance design automation and quality methodologies, including automated checks, regression analysis, dashboards, and team-level quality gates.

Skills

Must have

Experience: 3-6 years

Develop synthesizable RTL using Verilog/System Verilog for complex digital IPs and SoC subsystems.

Translate architecture specifications into scalable microarchitectures, integrating IPs and AMBA interfaces including AXI4, AXI4-Lite, AHB, and APB.

Drive RTL quality and design signoff, ensuring coding standards, methodology compliance, clean reviews, and first-pass silicon readiness.

Own closure of Lint, CDC, RDC, X-propagation, structural checks, synthesis issues, and design-rule violations.

Develop automation, dashboards, and quality metrics to improve RTL development, verification handoff, and signoff efficiency.

Nice to have

Candidates should be passionate about design quality, automation, and delivering production-ready RTL with minimal debug cycles.

Other

Languages

English: B2 Upper Intermediate

Seniority

Junior